1. Field of the Invention
The present invention relates to a process for forming self-aligned silicide.
2. Description of the Prior Art
Generally speaking, the salicide process is one of the most widely-used technologies in sub-micron (0.5 um) semiconductors, and the titanium (Ti) salicide process is the most frequently-used salicide technology. Therefore, the following descriptions will concentrate primarily on titanium salicide technology. Referring to FIG. 1a to FIG. 1e (Prior Art), a conventional process for forming self-aligned titanium salicide is shown. In FIG. 1a, a polysilicon layer is formed on substrate 5. The polysilicon layer is then patterned and etched using photo-resist layer 10 in order to define gate 12 of a device in an active region, and to define polysilicon line 16 on field oxide 14. As shown in FIG. 1b, impurities are implanted to form an LDD structure, and a non-conducting layer deposited over substrate 5 and etched back to form sidewall spacer 18 of gate 12 and polysilicon line 16. Then impurities are implanted to form source 20a and drain 20b on the side of gate 12 in substrate 5. As shown in FIG. 1c, after source 20a and drain 20b are formed, metal layer 22 is formed by sputtering which can react with silicon to form a silicide. Referring to FIG. 1d, the reactions of sputtered metal layer 22 and the silicon material on substrate 5 are activated by a thermal process, e.g. a rapid thermal process (RTP), so that silicide layer 24 is formed on the surface of polysilicon line 16 and in the active region. As shown in FIG. 1e, the unreacted metal is selectively etched away, so that only silicide layer 24 remains. Then a thermal process is used in order to improve the structure of formed salicide layer 24, and to reduce the resistance.
With the shrinking of semiconductor device dimensions and the planarization techniques ,e.g., chemical mechanical polishing (CMP), introduced in the process of fabricating ICs, several restrictions have arisen in conventional salicide processes:
(1) Although the metalization of a polysilicon gate/line can reduce the sheet resistance of the device, the sheet resistance can not be minimized when the line width continues to narrow. Therefore, a approach to solve the problem involves increasing the thickness of the formed self-aligned silicide layer, that is, to increase the thickness of the metal layer sputtered over the wafer so that a thicker self-aligned silicide layer can be formed on the surface of the polysilicon line and in the active region. While this method indeed reduces the problem caused by the narrower line width, a leackage current is unexpectedly increased at the same time. Since a smaller device must have a shallower junction in order to form an active region, the thickness of the formed self-aligned silicide layer in the active region has to be properly controlled. On the average, the thickness of the formed self-aligned silicide is maintained at around one-half of the juction depth in order to prevent unexpected leakage currents. Accordingly, conventional salicide processes can not satisfy these requirements at the same time. PA1 (2) Referring to FIG. 2(also Prior Art), because of the planarization techniques introduced into the process of IC production, especially CMP technology, the depths of the contact windows 30a and 30b will be quite different. In general, the polysilicon line regarded as an interconnect is often above field oxide 32. Therefore, the depth of contact window 30b is the shallower. The depth of contact window 30a is the deeper. The depth difference between the contact window 30a and 30b is about 2500 .ANG. to 5000 .ANG.. In this case, several problems will arise because of the different depths of the contact windows. When a process for contact etching is performed, because the depth of the contact windows 30b is shallower, the etching of the contact window 30b is first accomplished. At this time, the etching of the contact window 30a is not yet accomplished, so the etching process continues until the etching of the contact window 30a is also finished. However, long-term etching will cause the over-etching of the self-aligned silicide in contact window 30b. When the sputtered titanium is about 300 .ANG. to 500 .ANG., the formed self-aligned silicide is about 660 .ANG. to 1100 .ANG.. Further, when a general dry etching process is applied, with the selectivity ratio of the inter-layer dielectric (ILD) and silicide within 10, self-aligned suicide layer 33 in the contact window 30b is at least 250 .ANG. to 300 .ANG. over-etched by the end of the etching of the contact window 30a. Accordingly, a method to reduce this problem involves determining a high selectivity ratio of the oxide and the silicide. However, it is not easy to acquire proper etching solutions with high selectivity ratios for polysilicon lines and the salicide layer on them.